Office: Engineering East 264
Phone: (559) 278-4415
Mailing Address: 2320 E. San Ramon Ave., MS/EE 94, Fresno, CA 93740-8030
LinkedIn Profile: https://www.linkedin.com/in/nan-wang-b4b92712
Faculty Advisor: Asian Christian Student Organization
Spring 2017 Office Hours: Monday, Wednesday: 11am-1pm
More Information about Dr. Li:
- Search Committee, member, Department of Electrical and Computer Engineering
- LCOE Academic Affairs Committee, member, Lyles College of Engineering
- Microprocessor Systems and Labs
- Switching Theory and Logic Design
- Advanced Computer Architecture
- Advanced VLSI Design Seminar (G)
Editorial and Scholarly Review:
- Journal of Cyber-physical Systems, Editorial Board Member
- Reviewer, Plos One Journal, IET Micronano, IJSTR, IJCET-Inpressco and IJERT journals
- Session Chair, IEEE ICCC 2016
- TPC Member, Reviewer, IEEE ICCC 2016, IEEE WTS 2017, IEEE ISVLSI 2017, ACM GLSVLSI 2017, IEEE ICCN 2017
- International ICEEI 2017, ICITS 2017 and
- Ph.D., Computer Engineering (2008) - University of Louisiana at Lafayette, Lafayette, Louisiana
- Master of Science, Computer Engineering (2000) - University of Louisiana at Lafayette, Lafayette, Louisiana
- Bachelor of Science, Computer Science (1990) - Xiamen University, Xiamen, China
- 07/2000 to 05/2002 Hardware Engineer, Hughes Network System, San Diego
- 07/1990 to 05/1998 Hardware Engineer and Project Manager, BICE, Beijing
Membership & Professional Affiliations:
- IEEE, member
- ASEE, member
P.Zhao, J.McNeely, W. Kuang,N. Wang and Z. Wang, " Design of Sequential Elements for Low Power Clocking System”, Accepted for publication in IEEE Transaction on VLSI, 2010.
P. Zhao, J. McNeely, P. K. Golconda, S. Venigalla, N. Wang, M. Bayoumi, W. Kuang and L. Downey, “Low power Clocked-pseudo-nmos Flip-Flop for Level Conversion in Dual Supply Systems,” IEEE Transaction on VLSI, vol 17 (9) 2009.
N. Wang, A. Sanusi, P. Zhao, M. Elgamel and M. Bayoumi, “PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design,” Springer Journal of Signal and Processing, June, 2009.
N. Wang and M. Bayoumi, “System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies,” IET Transaction. on Comput. Digital Tech., Vol. 1, (1), 2007, pp. 1-8
Jiawen Xu and N. Wang, “ MSE Self-adaptive Quantizer of First-Class Signals”, Journal of Telemetry, Tracking, and Command, vol 1, 1997, China.
N. Wang and P. Valencia, “Traffic Allocation: An Efficient Adaptive Network-on-chip Router Algorithm Design”, in Proc. IEEE 2nd intl. Conf. ICCC 2016, Chengdu, China, October, 2016.
A. Sanusi, N. Wang and M. Bayoumi, “Guaranteeing QoS with the Pipelined Multi-Channel Central Caching NoC Communication Architecture,” in Proc. IEEE Intl. Conf. System-on-chip (SOCC 08’), September 2008, Newport Beach, California.
N. Wang, A. Sanusi, P. Zhao, M. Elgamel, and M. Bayoumi, “A Multi-Channel Central Caching Network-on-chip Communication Architecture Design,” in Proc. IEEE Conf. Signal and Processing (SIPs 07’), Shanghai, China, September 2007, pp. 487-492.
N. Wang, A. Sanusi and M. Bayoumi, “CTCNOC: A central caching network-on-chip communication architecture design,” in Proc. Intl. Conf. IP Based SOC Design, December 2006, Grenoble, France, pp. 49-52
N. Wang and M. Bayoumi, “DPCI: An Efficient Scalable System-on-chip Communication Architecture,” in Proc. Intl. Conf. IP Based SOC Design, December 2006, Grenoble, France, pp. 77-80
N. Wang and M. Bayoumi, “Dynamic fraction control bus: New SOC on-chip communication architecture design,” in Proc. IEEE Intl. Conf. System-on-chip (SOCC 05’), September 2005, Washington, DC, pp. 199-202
- System-on-chip/network-on-chip communication architecture
- Embedded system
- FPGA/ASIC design and implementation
- Real-time computing and VLSI design
- Mobile Ad Hoc Network (MANET)
- Wireless Network-on-chip Communication